The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed.
The scaling down of an IC device also faces challenges for performing a measurement on a complicated topography surface of a semiconductor wafer. For example, the complicated topography and the scaled down feature may cause a measurement error on a measurement tool, such as a scanning electron microscope (SEM) tool. Significant labor and time are therefore frequently needed to verify the measurement. Accordingly, what is needed is a method for verifying measurement data more efficiently and accurately